Phoronix has published the first independent benchmarks of AMD’s Zen 6 EPYC 9006 “Venice” processors against NVIDIA’s Arm-based Vera, and both Venice parts led across most of an HPC-heavy suite, with QuantLib showing the widest gap at 2.39x. The results are measured rather than modeled, but they come from one lab, an AMD-supplied reference platform and Vera numbers carried over from an October run, and the overall margin is much smaller than the best single result.
What was tested
The comparison set two dual-socket Venice configurations against a dual-socket Vera server. The EPYC 9996 carries 256 Zen 6c cores per socket at 2.55GHz base and 4.1GHz boost, with 1,024MB of L3 cache and a 600W default CPU power rating. The EPYC 9686F is the frequency-optimized part, with 96 full Zen 6 cores per socket. Vera brings 88 Olympus cores per socket, or 176 in the 2P box. Venice ran on AMD’s “Nigeria” reference platform with 16 channels of MRDIMM-12800 per socket, while Vera uses LPDDR5X-9600 in SOCAMM2 modules. Phoronix’s test system reports the 9686F peaking at 5.3GHz, though AMD’s SKU materials rate the part at 5.0GHz boost, and the review figure is the one used here.
The Vera results are not new. They come from Phoronix’s October HPC testing, which was done with unrestricted remote access, unlike the NVIDIA-curated session in May that limited which benchmarks could run and blocked power reporting.
What the numbers show
Across the full suite, the Phoronix Venice-versus-Vera geometric mean puts the 9686F at 1.13x Vera and the 9996 at 1.18x. Those are the figures to plan around. The 9686F has 192 cores against Vera’s 176, so per core it comes out about 4 percent ahead, a small but measured lead for x86 in exactly the category where Vera looked strongest this spring.
The large wins are workload-specific. QuantLib gave the 9996 its 2.39x result. Venice also overturned Vera’s October first-place finish in WRF weather modeling and widened Zen’s lead in LAMMPS. Vera still had the fastest meshing step in OpenFOAM’s large case, did well on libxsmm’s small matrix sizes, and placed second behind the 9996 in 7-Zip decompression.
Power
Venice drew more CPU power than the Vera pair, which in the October Vera HPC run averaged 842W with a 1,044W peak. Most of Venice’s performance-per-watt lead comes from the 9996, which posted the best efficiency in QuantLib, WRF and OpenFOAM. The 9686F was roughly level with Vera in at least one OpenFOAM case. These are CPU-reported figures, not wall power. A fully populated MRDIMM configuration draws far more than Vera’s LPDDR5X, which NVIDIA puts at around 50W. So the efficiency lead is measured at the socket and untested at the wall.
Nearly three times the cores, 1.18x the throughput
AMD’s own Vera comparisons are much bolder than this. Its 3.3x rack-level figure inside a 100kW envelope is estimated: according to its rack-level methodology document, Vera’s numbers were scaled up from Grace by 1.63x using Phoronix’s curated May data, and Venice’s were projected at 1.7x over the EPYC 9965. Its 2.24x SPECrate 2026 integer figure is also an AMD estimate.
The measured data tells a narrower story for HPC. A dual 9996 has 512 cores, 2.9 times Vera’s 176, and on this suite it delivered 1.18x the performance. Many of these workloads are limited by memory bandwidth, and core count does little for them. AMD’s rack model assumes throughput grows with density. That may hold for integer throughput, Java or agent sandboxes, none of which this review covered. For simulation codes, nothing published so far supports it. Anyone sizing racks against the power demands of AI datacenters should use the geomean, not the projection.
What ships when
EPYC 9006 SP7 processors, including both chips tested, have been shipping since November 10. Phoronix expects Venice to run on current distributions such as Ubuntu 26.04 LTS and RHEL 10, so admins locking down a fresh Ubuntu 26.04.1 LTS install shouldn’t need an out-of-tree stack. The rest of the family is planned:
- SP8 parts are due in the first half of 2027. Giga Computing has said its SP8 systems will ship in March 2027.
- Venice-X, with 3D V-Cache, and the LPDDR5X-based EPYC 9006 LP “Verano” are targeted for the second half of 2027.
- Intel’s answer, Xeon Diamond Rapids, is expected in 2027.
Verano is the comparison to watch. It uses the same SOCAMM2 memory as Vera, which would separate the core architecture from the memory subsystem in a way this round of testing couldn’t.
